Integrated Circuits

ET2024

INTERPOLATION DEVICE

(Interpolation factors of 2X or 4X)

FEATURES

• Interpolation factor pin selectable (2x/4x)
• Index gating pin selectable (90/180 electrical degrees of interpolated pulse)
• Leading edge of gated index pulse occurs at 270 electrical degrees of analog input cycle, regardless of interpolation factor selected
• Interfaces directly with ET2010 Analog Signal Processor and ET7272 Line Driver
• Single supply operation
• Handles Sine/Cosine inputs from DC to125KHz
• Sine/Cosine input voltage range 400mVpp to 4Vpp on 2.5VDC reference
• Outputs are NPN Collector with 4K pull-up; sink up to 4mA external load
• Outputs TTL and CMOS compatible
  

See pin descriptions on last sheet.

This part is available in a 20 lead SSOP package, or as die.

DESCRIPTION

This ET2024 is a monolithic bipolar integrated circuit designed to facilitate increased resolution in optical encoder applications by converting the incoming sine and cosine signals to an interpolated quadrature digital output at 2 or 4 times the input frequency. Please refer to the Timing Diagram. The device inputs receive photodiode signals which have been amplified and conditioned to optimize the interpolation function. This conditioning may be obtained from a companion device, the analog signal processor, ET2010. Following interpolation processing by the ET2024, the output signal can be fed into a line driver device, such as the ET7272, for driving extended loads. Please see the Application Circuit. In addition to processing the data channel information, the ET2024 provides a channel for the index signal which controls the gating of the index pulse relative to the 0° and 90° input waveforms. Index gating is provided to generate a pulse that commences at 270 electrical degrees of the analog input cycle. Width of the index pulse is either 90 or 180 electrical degrees of the interpolated pulse (pin selectable).

DESIGN SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values given at V_CC=5V, T_A = 25°C, and V_IN = 1.6V_(P-P).

Block Diagram

Application

Please refer also to the block diagram. The sine and cosine inputs (0_SIG, 90_SIG, 180_SIG) should be in the range of 400mVpp to 4Vpp, with a DC offset of 2.5V . Care must be taken to limit the noise on the analog inputs to avoid spurious signals at the outputs. The hysteresis of the phase comparators is 20mV, and while a large input signal may seem advantageous, it is so only as long as the noise is well below the 20mV level. Therefore, from a practical standpoint, the input levels are often limited to the 1.5Vpp range. The ET2024 accepts the DC offset of the analog signals as an input at the SIG_REF pin. The outputs are NPN collectors with 4K pull-ups. For high-frequency applications, output rise time can be reduced by addition of external pull-up resistors as low as 1.5K, as long as the 4mA limit on external loading is not exceeded. For applications that use photodiode sensing, ETIC offers the ET2010 Analog Signal Processor for generating sine/cosine signals compatible with the ET2024. Please refer to the Application Circuit, which handles inputs from photodiode sensors and processes them through to line driver outputs.

Application Circuit

Disk Optimization

The placement of the index feature on the encoder disk can be optimized, depending on the variety of interpolation factors and index widths that will be used with a given disk. Please refer to Timing Diagram. If a disk is to be used in both 2X and 4x interpolation modes, and with both Z90 and Z180 index gating modes, then the index feature should be centered at 315 degrees of the analog input cycle. If the application is designed uniquely for 4x interpolation in the Z90 mode, the index feature on the disk should be centered at 281.25 degrees. Optimization of the disk in this manner affords a wider margin for misalignment, and can therefore enhance the ease of assembly in volume production.

Timing Diagram

Pin Descriptions