East Texas
Integrated Circuits

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Integrated Circuits

ET0412

Dual Emitter Phototransistor Medium-High Gain

FEATURES

Spectral response tailored to perform well with either GaAs or GaAlAs emitters
Convenience of bonding the emitter from either side of the die
Collector voltage to 30V
Base pad available for bonding
Designed specifically for mounting side by side for use in sensing optical tracks in encoder applications

DESCRIPTION

The ET0412 phototransistor is fabricated using silicon planar diffused technology. The die is silicon nitride passivated for reliability, and anti-reflection coated to enhance light absorption. The unique feature of this die is that the transistor has two emitters. While both emitters share a common base, the light sensitive area, they allow the user the flexibility of making connection from either side of the die. This is most helpful when multiple ET0412 die are mounted end to end to form a 1 x N array. The circuit pattern on the substrate may be made less dense, as only every other die will have an emitter connection on a given side of the array. This is convenient in those packages such as leadless chip carriers where the external package terminations are on opposite sides of the package. Routing the connections from the various emitters then becomes very straightforward.

One other advantage of this design is that the emitters are quite small, and as a result, there is a bit of a speed improvement over typical phototransistor die. Where illumination levels are adequate, applications now using a traditional single emitter die may find this die to have better frequency response. Please request Application Note App D4 for details. Applications include optical encoders and industrial controls.

Standard thickness is 15 mils. Die can be sawed in various array configurations.

Pad	Description/Use
Base	Base is normally left open, biased only by the light incident on the “sensor area”
Emitter 1, Emitter 2	The two pads, on opposite sides of the die, provide connection to the two emitters of the transistor structure.
Light Shield	These metal areas are intended to further define the “sensitive area” of the device, to confine the region of carrier absorption. These pads are at the same potential as the collector of the device, but are not intended to be used to connect to the collector. The intended collector connection is the backside of the die, which is metallized to provide a low resistance interface.

ABSOLUTE MAXIMUM RATINGS
Parameter	Symbol	Min.	Max.	Units	Ref.
Operating Temperature Range	T_A	-55	125	°C	(Note 1)
Collector-Emitter Voltage	V_CE	-	30	V	-
Emitter-Collector Voltage	V_EC	-	7	V	-
Power Dissipation	P_D	-	50	mW	(Note 1)
Continuous Collector Current	I_C	-	20	mA	(Note 1)

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, typical values given at V_CE=5V, T_A = 25°C, H=0mW/cm².

Parameters	Symbol	Min.	Typ.	Max.	Units	Test Conditions
Collector Dark Current	I_D	-	<15	40	nA	V_CE = 10V
Collector-Emitter Breakdown Voltage	V_CE	30	-	-	V	I_C = 100µA
Collector-Base Breakdown Voltage	V_CB	40	-	-	V	I_C = 100µA
Collector-Emitter Saturation Voltage	V_SAT	-	140	240	mV	I_C = 1mA, IB = 40µA, (Note 2)
Emitter-Collector Breakdown Voltage	V_EC	7.0	7.6	-	V	I_C = 10µA
Responsivity	R	-	.32	-	A/W	H = 5 mW/cm2 (Note 3)
Current Gain	h_FE	460	-	1200	-	I_C = 100 µA (Note 2)

AC SWITCHING CHARACTERISTICS

Values given at V_CC = 5V, T_A = 25°C, R_{EMITTER LOAD} = 1000 ohms. See Test Setup diagram and example waveform.

Parameters	Symbol	Min.	Typ.	Max.	Units	Test Conditions
Rise Time	T_R	-	7	-	µs	(Note 3)
Fall Time	T_F	-	9	-	µs	(Note 3)

NOTES:

This value is very dependent on the thermal impedance of subsequent packaging techniques.
For test, base current is forced at base pad rather than created by illumination.
These values are typical for the process and are not tested.

ETIC RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME TO IMPROVE THE DESIGN AND TO SUPPLY THE BEST PRODUCT.